vishay siliconix si1400dl document number: 71179 s10-0721-rev. d, 29-mar-10 www.vishay.com 1 n-channel 20 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet : 2.5 v rated ? compliant to rohs directive 2002/95/ec product summary v ds (v) r ds(on) ( )i d (a) - 20 0.150 at v gs = 4.5 v 1.7 0.235 at v gs = 2.5 v 1.3 ordering information: si1400dl-t1-e3 (lead (pb)-free) SI1400DL-T1-GE3 (lead (pb)-free and halogen-free) sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view d d g d d s marking code nd xx lot traceability and date code part # code yy notes: a. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 5 s steady state unit drain-source voltage v ds 20 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) a t a = 25 c i d 1.7 1.6 a t a = 85 c 1.2 1.0 pulsed drain current i dm 5 continuous source current (diode conduction) a i s 0.8 0.8 maximum power dissipation a t a = 25 c p d 0.625 0.568 w t a = 85 c 0.40 0.295 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 5 s r thja 165 200 c/w steady state 180 220 maximum junction-to-foot (drain) steady state r thjf 105 130
www.vishay.com 2 document number: 71179 s10-0721-rev. d, 29-mar-10 vishay siliconix si1400dl notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.6 v gate-body leakage i gss v ds = 0 v, v gs = 12 v 100 na zero gate voltage drain current i dss v ds = 16 v, v gs = 0 v 1 a v ds = 16 v, v gs = 0 v, t j = 85 c 5 on-state drain current a i d(on) v ds 5 v, v gs = 4.5 v 2 a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 1.7 a 0.123 0.150 v gs = 2.5 v, i d = 1.3 a 0.195 0.235 forward transconductance a g fs v ds = 10 v, i d = 1.7 a 5 s diode forward voltage a v sd i s = 0.8 a, v gs = 0 v 0.78 1.1 v dynamic b total gate charge q g v ds = 10 v, v gs = 4.5 v, i d = 1.7 a 2.1 4.0 nc gate-source charge q gs 0.3 gate-drain charge q gd 0.4 tu r n - o n d e l ay t i m e t d(on) v dd = 10 v, r l = 20 i d ? 1 a, v gen = 4.5 v, r g = 6 10 17 ns rise time t r 30 50 turn-off delay time t d(off) 14 25 fall time t f 815 source-drain reverse recovery time t rr i f = 0.8 a, di/dt = 100 a/s 30 50 output characteristics 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v gs = 4.5 v thr u 3 v 2 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 1.5 v 2.5 v transfer characteristics 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 t c = 125 c -55 c 25 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d
document number: 71179 s10-0721-rev. d, 29-mar-10 www.vishay.com 3 vishay siliconix si1400dl typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage - on-resistance ( ) r ds(on) 0 0.1 0.2 0.3 0.4 0.5 012345 i d - drain c u rrent (a) v gs = 2.5 v v gs = 4.5 v 0 0.9 1. 8 2.7 3.6 4.5 0 0.5 1.0 1.5 2.0 2.5 v ds = 10 v i d = 1.7 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs 0 0.2 0.4 0.6 0. 8 1.0 1.2 t j = 150 c t j = 25 c 10 0.1 v sd -) v ( e g a t l o v n i a r d - o t - e c r u o s - so u rce c u rrent (a) i s 1 capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 60 120 1 8 0 240 300 04 8 12 16 20 v ds - drain-to-so u rce v oltage ( v ) c rss c oss c iss c - capacitance (pf) 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 1.7 a t j - j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on) 0 0.0 8 0.16 0.24 0.32 0.40 012345 i d = 1.7 a - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v )
www.vishay.com 4 document number: 71179 s10-0721-rev. d, 29-mar-10 vishay siliconix si1400dl typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71179 . threshold voltage - 0.6 - 0.4 - 0.2 0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ariance ( v ) v gs(th) t j - temperat u re (c) single pulse power 0 6 10 2 4 po w er ( w ) time (s) 8 130 10 0.01 0.1 normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 400 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1
dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an813 vishay siliconix document number: 71236 12-dec-03 www.vishay.com 1 single-channel little foot sc-70 3-pin and 6-pin mosfet recommended pad pattern and thermal peformance introduction basic pad patterns this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for single-channel little foot power mosfets in the sc-70 package. these new vishay siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 350 ma) need to be switched, either directly or by using a level shift configuration. vishay provides these single devices with a range of on-resistance specifications and in both traditional 3-pin and new 6-pin versions. the new 6-pin sc-70 package enables improved on-resistance values and enhanced thermal performance compared to the 3-pin package. pin-out figure 1 shows the pin-out description and pin 1 identification for the single-channel sc-70 device in both 3-pin and 6-pin configurations. the pin-out of the 6-pin device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. sot-323 sc-70 (3-leads) 1 2 3 top view g s d sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view d d g figure 1. for package dimensions see outline drawings: sc-70 (3-leads) ( http://www.vishay.com/doc?71153 ) sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the basic pad layout and dimensions for the 3-pin sc-70 and the 6-pin sc-70. these pad patterns are sufficient for the low-power applications for which this package is intended. increasing the pad pattern has little effect on thermal resistance for the 3-pin device, reducing it by only 10% to 15%. but for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 35% when using a 1-inch square with full copper on both sides of the printed circuit board (pcb). the availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the pcb and external environment. evaluation boards for the single sc70-3 and sc70-6 figure 2 shows the 3-pin and 6-pin sc-70 evaluation boards (evb). both measure 0.6 inches by 0.5 inches. their copper pad traces are the same as described in the previous section, basic pad patterns . both boards allow interrogation from the outer pins to 6-pin dip connections, permitting test sockets to be used in evaluation testing. the thermal performance of the single sc-70 has been measured on the evb for both the 3-pin and 6-pin devices, the results shown in figures 3 and 4. the minimum recommended footprint on the evaluation board was compared with the industry standard of 1-inch square fr4 pcb with copper on both sides of the board. figure 2. front of board sc70-3 front of board sc70-6 back of board, sc70-3 and sc70-6 chipfet chipfet vishay.com
an813 vishay siliconix www.vishay.com 2 document number: 71236 12-dec-03 thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the 3-pin sc-70 measured as junction-to-foot thermal resistance is 285 c/w typical, 340 c/w maximum. junction-to-foot thermal resistance for the 6-pin sc70-6 is 105 c/w typical, 130 c/w maximum ? a nearly two-thirds reduction compared with the 3-pin device. the ?foot? is the drain lead of the device as it connects with the body. this improved performance is obtained by the increase in drain leads from one to four on the 6-pin sc-70. note that these numbers are somewhat higher than other little foot devices due to the limited thermal performance of the alloy 42 lead-frame compared with a standard copper lead-frame. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the single 3-pin sc-70 is 360 c/w steady state, compared with 180 c/w for the 6-pin sc-70. maximum ratings are 430 c/w for the 3-pin device versus 220 c/w for the 6-pin device. all figures are based on the 1-inch square fr4 test board.the following table shows how the thermal resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. sc-70 (3-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 360 o c w p d 347 mw p d t j(max) t a r ja p d 150 o c 60 o c 360 o c w p d 250 mw sc-70 (6-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 180 o c w p d 694 mw p d t j(max) t a r ja p d 150 o c 60 o c 180 o c w p d 500 mw note: although they are intended for low-power applications, devices in the 6-pin sc-70 will handle power dissipation in excess of 0.5 w. testing to aid comparison further, figures 3 and 4 illustrate single-channel sc-70 thermal performance on two different board sizes and two dif ferent pad patterns. the results display the thermal performance out to steady state and produce a graphic account of the thermal performance variation between the two packages. the measured steady state values of r ja for the single 3-pin and 6-pin sc-70 are as follows: little foot sc-70 3-pin 6-pin 1) minimum recommended pad pattern (see figure 4) on the evb. 410.31 c/w 329.7 c/w 2) industry standard 1? square pcb with maximum copper both sides. 360 c/w 211.8 c/w the results show that designers can reduce thermal resistance r ja on the order of 20% simply by using the 6-pin device rather than the 3-pin device. in this example, a 80 c/w reduction was achieved without an increase in board area. if increasing board size is an option, a further 118 c/w reduction could be obtained by utilizing a 1-inch square pcb area. time (secs) figure 3. comparison of sc70-3 and sc70-6 on evb thermal resistance (c/w) 0 1 400 80 160 100 1000 240 10 10 -1 10 -2 10 -3 10 -4 10 -5 0.5 in x 0.6 in evb 3-pin 320 time (secs) figure 4. comparison of sc70-3 and sc70-6 on 1? square fr4 pcb thermal resistance (c/w) 0 1 400 80 160 100 1000 240 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square fr4 pcb 320 6-pin 3-pin 6-pin
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
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